1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as a system LSI incorporating DRAMs, a method of manufacturing the same, and a cell size calculation method for DRAM memory cells.
2. Description of the Prior Art
In recent years, a DRAM mixing or hybrid system LSI which integrates a logic such as processor, ASIC, or the like, and a large-scale DRAM on a common semiconductor substrate has been applied for many purposes. In such a system LSI, an internal data bus of multiple bits, e.g. 128-512 bits, makes an interconnection between the logic and the DRAM, thus achieving a data transmission speed which is higher by one to two orders, as compared to a case that a commercially available DRAM and a logic each having a small number of terminals are connected with each other on a common printed circuit board.
In addition, with respect to the logic, the number of external input pins may be reduced as compared to a system configuration which mounts externally the commercially available DRAMs. Further, a DRAM block is connected to a logic via an internal wiring inside the system LSI. Since the length of the internal wiring is sufficiently shorter than that of wirings on the printed circuit board, and also has a small parasitic impedance, charging and discharging currents can be drastically reduced, and signal transmissions can be carried out at high speed.
From these reasons, the DRAM hybrid system LSI has contributed greatly to the high performance of intelligence apparatuses that deal with a large amount of data of 3-D graphic processing, image and voice processing, and the like.
FIG. 17 is a schematic block diagram illustrating a configuration example of a conventional semiconductor integrated circuit device, which designates a DRAM mixing or hybrid system LSI. In FIG. 17, reference numeral 100 designates a power supply pin terminal for feeding power supply potential exVdd; 101 designates a large scale logic (LG); 102 designates an analog core (ACR); 103 designates a DRAM core (MCR); 104 designates a test interface circuit (TIC); 105 designates a first external pin terminal group (LPGA); 106 designates a second external pin terminal group (APG); and 107 designates a test pin terminal group (TPG).
The aforementioned system LSI includes: the large scale logic 101, connected to the first external pin terminal group, for executing a commanded processing; the analog core 102, connected between the large scale logic 101 and the second external pin terminal group 106, for executing a processing of analog signals; the DRAM core 103, connected to the large scale logic 101 via internal wirings, for storing data required by the large scale logic 101; and a test interface circuit 104 for executing a test operation for the DRAM core 103 through the test pin terminal group 107 while separating the large scale logic 101 and the DRAM upon a test mode. The DRAM core 103 receives a power supply voltage exVDD via the power supply pin terminal 100.
The analog core 102 includes a Phase-Locked Loop (PLL) for generating an internal clock signal; an analog/digital (A/D) converter for converting an externally inputted analog signal to a digital signal; and a digital/analog (D/A) converter for converting a digital signal supplied from the large scale logic 101 to an analog signal to be outputted.
FIG. 18 is a sectional schematic illustration taken along an arbitrary line in a large scale logic unit during a conventional DRAM-logic mixing process. In FIG. 18, reference numeral 201 designates a semiconductor substrate; 202 designates a first interlayer dielectric; 203a and 203b each designate a second interlayer dielectric; 204 designates a third interlayer dielectric; 205 designates a fourth interlayer dielectric; 206 designates a cover film; 211 designates a word line; 221 designates a bit line; 222 designates a first metal wiring; 223 designates a second metal wiring; 224 designates a third metal wiring; 231 designates a via plug such as tungsten W; 241 designates a contact hole; 242 designates a first through hole for connecting the first metal wiring 222 with the second metal wiring 223; and 243 designates a second through hole for connecting the second metal wiring 223 with the third metal wiring 224.
In FIG. 18, an n-channel or p-channel MOS transistor is first formed on the semiconductor substrate electrically separated by trench isolation. The gate electrode is formed by a wiring layer made of a silicon containing material, for example, polysilicon doped with an impurity or doped polysilicon, polycide such as tungsten silicide (WSix), and the like, and serves as the word line 211 through a microfabrication.
Metal wiring layers for multilevel metallization are formed by a metal such as aluminum Al or an alloy containing copper Cu therein on the upper layer of the MOS transistor with interposing the first to fourth interlayer dielectrics 202-205. These wiring layers are micro-fabricated independently to form the first metal wiring 222, second metal wiring 223, and third metal wiring 224.
These metal wirings 222-224 are electrically connected to the wiring layer of the bit line 221 formed by a material such as tungsten via the via plug 231 in which tungsten W or the like is buried in the contact hole 241 and through holes 242 and 243.
Note that the above-described bit line 221 is not required in a perfect CMOS logic process which mixes no DRAMs.
FIG. 19 is a schematic diagram of a memory cell array section of a DRAM core in a conventional semiconductor integrated circuit device, and FIG. 20 is a sectional schematic illustration taken along an arbitrary line in the longitudinal direction of the memory cell array of FIG. 19. In FIG. 19, reference numeral 301 designates a cell plate electrode CP; 302 designates a storage node contact; 303 designates a bit line contact; 305 designates a sense amplifier S/A; 310 designates a sub-word driver range (odd); 311 designates a sub-word driver range (even); 315 and 316 designate main word lines MWL less than i greater than  and MWL less than i+1 greater than  (i=natural number), respectively; BL and ZBL designate a non-inversion bit line and an inversion bit line, respectively; and WL designates a word line, which connects with the main word line MWL via the logic gate.
The memory cell is typically composed of a capacitor for storing an electric charge and a field effect transistor (FET) or MOS transistor operating as a cell selection switch, and is called one transistor type. The gate electrode of this transistor is connected to the word line WL which feeds a selection signal of the memory cell, and controls the opening and closing of the memory cell. On the other hand, the drain of the transistor is connected to the bit lines BL and ZBL for cell information intake which are wired perpendicularly to the word line WL, and exchanges of data between memory cell and read or write circuit will be carried out through the drain.
In FIG. 20, the reference numeral 401 designates a semiconductor substrate 401; 402 designates a trench isolation region; 403 designates a word line; 403a designates a transistor gate wiring; 405 designates a configuration dummy bit line; 406 designates a bit line; 407 designates a storage node; 408 designates a cell plate electrode CP; 409a, 409b, and 411 each designate a contact buried by a via plug made of tungsten W; 410 designates a first metal wiring serving as a main word line; 412 designates a second metal wiring serving as a VCP power supply line; 421 designates a first interlayer dielectric; 422a and 422b each designate a second interlayer dielectric; and 423 designates a third interlayer dielectric.
Incidentally, a capacitor dielectric is formed between the storage node 407 and the cell plate CP 408, and these components construct a stacked capacitor to store a signal electric charge.
The operation will be next described below.
The sense amplifier S/A for amplifying a micro-signal is connected to each of the bit lines BL and ZBL, and the input/output of data to the external is carried-out through a multiplexer for selecting a specific bit line out of a plurality of bit lines BL and ZBL. A flip-flop is normally employed for the sense amplifier S/A, and a pair of bit line signals are inputted as a differential signal. The voltage of a reference signal which pairs with the bit line signal is generated through a dummy cell which is constructed by the same circuit as that of the memory cell.
On reading of the cell data, for example, after the bit line is changed to one potential, the word line WL to be selected is activated by a word line driver including the sub-word driver ranges 310 and 311, thus reading the charge stored in the capacitor to the bit line BL, while the reference voltage is given to the bit line ZBL pairing with the bit line BL. The sense amplifier S/A amplifies a voltage difference of the micro-signal which is caused by a difference between the bit line voltage on reading the cell data and the reference voltage, and the resultant is transferred to an output circuit through the multiplexer.
On the other hand, on writing of the cell data, the word line WL to be selected is activated and turns on or conduct a cell selection transistor, and it is carried out by taking in the cell a high or low potential level on the bit lines BL and ZBL.
A method of manufacturing the conventional semiconductor integrated circuit as shown in FIG. 20 is schematically described below.
A trench isolation region is first formed in the semiconductor substrate 401 to define an active region serving as a transistor region, and a transistor section is created through a plurality of ion implantation processes involving a resist pattern formation, and the word line 403 is formed on the transistor section. The first interlayer dielectric 421 is deposited on top, and a desired contact hole is opened by a microfabrication including photolithography and etching processes. Then a wiring layer is deposited on top by sputtering and the bit line 406 and configuration dummy bit line 405 are formed by the microfabrication as well.
Further, the second interlayer dielectric 422a is deposited on this topography and then opened by a desired contact hole. The storage node 407 is formed to be thoroughly in contact with the substrate 401. Further, the cell plate electrode 408 is formed on the storage node 407 with sandwiching the capacitor dielectric, finally effecting a conventional stacked capacitor structure.
Thereafter, the second interlayer dielectric 422b is formed on the topography and opened by through holes, and the via plugs made of tungsten W are buried in the through holes to form the contacts 409a and 409b. Then, the first metal wiring 410 is formed to electrically contact these contacts 409a and 409b, and finally, the third interlayer dielectric 423 is deposited and the second metal wiring 412 is finally formed on top.
Here, it should be noted that as to the layout of the memory cell of FIG. 19, a length where a minimum pitch length is projected to the column or bit line direction is equal to half of a layout pitch in the column direction of the memory cell. Note that the minimum pitch length is found when the bit line contacts are linked with each other in the slant direction. In addition, the bit line pair connecting the sense amplifier has a folded bit line configuration with strong noise resistance.
In the above-described cell size calculation method of DRAM memory cells, when it is designated by a minimum microfabrication dimension or F called feature size in design, a size ratio (length-to-width) is typically approximate to 2:1, and a 8F2 cell having 2F in width size and 4F in length size is employed.
In FIG. 20, an n-channel or p-channel MOS transistor constructing a memory cell transistor and an array control circuit is created on the semiconductor substrate 401 that is separated electrically by the trench isolation region 402. The gate electrode is formed by a wiring layer made of a silicon containing material such as doped polysilicon or polycide, e.g. WSix, which is the same layer as that of the word line 403, as well as the gate wiring 403a. 
On top of this, the bit line 406 and a capacitor structure including layers of the storage node 407 and the cell plate 408 are formed. The bit line 406 is formed by a silicon containing material, for example, doped polysilicon or polycide such as WSix. Further, a multi-level metal wiring layer having the same structure as that of the logic unit or the first metal wiring 410 and second metal wiring 412 is formed through the contact 411 on the uppermost layer.
As shown in FIG. 20, a 3-D capacitor structure having such a complicated three dimensional structure as heightens the storage node is formed when the capacitor area is still larger to ensure the capacitance in the stacked capacitor. In this case, a large step height, however, occurs between the memory array section and the other peripheral circuit section, which makes it difficult to tight the wiring pitch in the metal wiring layers. For this reason, it is required to reduce drastically the aforementioned step height by introduction of a planarization process based on CMP (Chemical Mechanical Polishing).
Since the conventional semiconductor integrated circuit device, method of manufacturing the same, and cell size calculation method of DRAM memory cells are configured as described above, for example, in the DRAM hybrid system LSI, it is required to add newly a process step of forming wirings and electrodes which construct the capacitor section in the DRAM core and a planarization process step of reducing the step difference caused by the 3-D structure capacitor to normal CMOS logic processes. This leads to a large increase of the number of the total process steps, resulting in boosting the general chip cost.
On the other hand, there is an SRAM as a hybrid memory that can be formed by way of complete CMOS logic processes, and the SRAM has been applied to cache memories, register file memories, and the like with respect to a conventional processor.
Since the SRAM eliminates the following items: a refresh operation, which is necessary for DRAMS, every a refresh period of time; and a complicated memory control related to the refresh such that an access to the memory during refreshing must be on standby till the end of the refresh cycle, it is employed as a main memory for simplicity of the system configuration in portable information terminals and the like in the middle of serious requests for down sizing.
However, there is a drastically improved function in the portable information terminals, for example, managing even moving pictures recently, which requires a further large capacity memory.
That is, the shrinkage of the memory size in DRAMs makes progress in accordance with the development of microfabrication processes; for example, a cell size of 0.3 xcexcm 2 has been already achieved in 0.18 xcexcm DRAM processes. On the other hand, the memory cell of the SRAM is constructed by six transistors together with p-channel and n-channel ones; even when the microfabrication processes make progress, the shrinkage of the memory size does not develop as much as that of DRAMs because of the restriction of an isolation distance between p-well and n-well; therefore, the memory size of the SRAM in 0.18 xcexcm CMOS logic processes is still the extent of 7 xcexcm2, which extends to twenty times the memory size of DRAMs as it stands.
As described above, since the chip size of the SRAM cannot help enlarging drastically in accordance with its large capacity development, which makes it hard extremely to hybridize 4 M (mega) or more SRAMs with logic circuits.
The present invention is implemented to solve the foregoing drawbacks. It is therefor an object of the present invention to provide a semiconductor integrated circuit device and a method of manufacturing the same, and a cell size calculation method of a DRAM memory cell in which the cell size of a DRAM memory cell is not as small as that of a typical DRAM memory cell but smaller sufficiently than that of a SRAM memory cell, and may be formed through a certain process near a process for CMOS logics, thus achieving a mixing memory capable of even a large capacity which is difficult for SRAMs.
A semiconductor integrated circuit device according to he present invention has the following characteristics:
Since the cell size of a DRAM memory cell is configured o be not as small as the typical memory cell size but smaller sufficiently than that of the SRAM in order to ensure a capacitor capacitance required for DRAM operations, a sufficiently large capacitor area is obtained even in a planar-type capacitor structure, and further a cell plate may be formed in the same layer as that of a word line serving as a gate electrode of a memory cell transistor; and
furthermore, since a storage node for the capacitor is formed by a diffusion region on a semiconductor substrate, a step height may be eliminated completely between a memory cell array section and a peripheral circuit section.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size;
a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and
a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of the active area in which the cell plate electrode is not formed and serves as a gate electrode of the field effect transistor on the active area, the word line pattern being formed through a gate oxide at a predetermined interval,
wherein the layout of a cell array of the memory cells is provided by a closest packing cell configuration.
Here, the pitch of the memory cell in the transverse direction may be loosened and at least two bit lines may be arranged for each pitch of the memory cell in the longitudinal direction.
The thickness of the capacitor dielectric may be the same as that of the gate oxide.
The capacitor dielectric may be made thinner than the gate oxide.
Another first conductance-type diffusion having a highly doped diffusion region may be provided under the diffusion region.
The capacitor structure may be a trench structure.
It is preferable that the first conductance-type is p-type and the second conductance-type is n-type, or the first conductance-type is n-type and that the second conductance-type is p-type.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device comprising:
a first step of forming an active area and a device isolation region on the main surface of a semiconductor substrate and creating a field pattern of a memory cell array having a plurality of memory cells;
a second step of carrying out an impurity implant on the main surface to form a first conductance type well region which extends to a certain depth;
a third step of creating a resist pattern which covers art of the active area to form a second conductance-type diffusion region by carrying out the impurity implant through the resist pattern;
a fourth step of forming in turn a insulating film and an wiring layer each having a predetermined thickness after removing the resist pattern;
a fifth step of etching the wiring layer through a desired pattern created on the top for a microfabrication to form a gate electrode of a field effect transistor and a cell plate electrode;
a sixth step of forming insulating sidewalls to the gate electrode and the cell plate to form a highly doped diffusion region with the second conductance-type through a high-dose ion implant;
a seventh step of forming a first interlayer dielectric to open a contact hole therein by a microfabrication; and
a eighth step of forming a metal wiring layer and creating a metal wiring from the wiring layer through a microfabrication.
Here, the third step may include a step of forming a highly doped diffusion region with the first conductance-type extending under the second conductance-type diffusion region.
The second step may include a step of forming another insulating film after formation of the well region and the third step includes a step of removing the another insulating film after formation of the second conductance-type diffusion region
The first step may include a step of forming a trench within a section of the memory cell array.
It is preferable that the first conductance-type is p-type and the second conductance-type is n-type, or that the first conductance-type is n-type and the second conductance-type is p-type.
According to a third aspect of the present invention, there is provided a memory size calculation method for DRAM memory cells characterized in that a cell size of a planar-type capacitor in a memory cell laid out in accordance with a closest packing cell configuration is found based on a minimum microfabrication dimension.
According to a fourth aspect of the present invention, there is provided a memory size calculation method for DRAM memory cells that when the cell sizes in the transverse and longitudinal directions are represented nxF and nyF, respectively, based on a minimum microfabrication dimension F, and a capacitor area for a signal and a cell area are represented Scap and Scell, respectively, respectively, and under the conditions of naxe2x89xa72.5, nxxe2x89xa72 (integer), and nyxe2x89xa72 (integer), the na, nx, and ny values are derived so as to bring the cell area Scell to a minimum based on the following formulae (1) and (2):
Scap=(nxFxe2x88x92F)xc2x7(nyFxe2x88x92naFxe2x88x920.5F)xe2x80x83xe2x80x83(1)
Scell=nxFxc2x7nyFxe2x80x83xe2x80x83(2)